📜  如何在 Verilog 中使用 for 循环 - 无论代码示例

📅  最后修改于: 2022-03-11 14:56:08.592000             🧑  作者: Mango

代码示例1
module my_design;
    integer i;

    initial begin
        // Note that ++ operator does not exist in Verilog !
        for (i = 0; i < 10; i = i + 1) begin
            $display ("Current loop#%0d ", i);
        end
    end
endmodule