-- sll,srl,rol, etc. cannot be used on a std_logic_vector until VHDL 2008
-- one workaround is to convert to the unsigned type from ieee.numeric_std,
-- carry out the shift and then convert back to std_logic_vector

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;

...
Dout <= std_logic_vector(unsigned(Din) sll 1);