前提条件– ALU和数据路径
在本节中,我们将讨论数据路径之间的区别。这些数据路径是:
- 单周期
- 多周期
- 管道
在单周期中,时钟周期时间对于指令来说足够长,而在多周期中,而流水线时钟周期时间对于指令来说足够短。
现在,它们之间的区别如下:
Single Cycle | Multiple Cycle | Pipeline |
---|---|---|
Single Cycle has one CPI (clock cycle per instruction). | Multiple cycle have variable number of CPI (Clock Cycle Per Instruction). | In pipeline, there is fixed number of CPI (Clock Cycle Per Instruction). |
Single cycle have no instructions subdivided. | Multiple cycle have arbitrary number of instructions subdivided. | pipeline also have instructions subdivided one step per pipeline stage. |
In Single cycle, there is executed one instruction at the same time. | In Multiple cycle, there is also executed one instruction at same time. | But in pipeline, many instructions are executed at the same time. |
Extra registers are not used in single cycle. | But in multiple cycle, extra registers are used. | Extra registers are also used in pipeline. |
In single cycle, clock cycle time is long. | In multiple cycle, clock cycle time is short. | In pipeline, clock cycle time is also short. |
There is no overlapping in single cycle. | In multiple cycle, there is also no overlapping. | In pipeline, there is overlap instruction execution. |