中断是由CPU以外的组件引起的事件。它指示需要立即关注的外部事件的CPU。中断异步发生。可屏蔽和不可屏蔽中断是两种类型的中断。
1.可屏蔽中断:
可由CPU指令禁用或忽略的中断称为可屏蔽中断,该中断可沿触发或电平触发或电平触发。
Eg:
RST6.5,RST7.5,RST5.5 of 8085
2.不可屏蔽中断:
不能被CPU指令禁止或忽略的中断称为不可屏蔽中断。当响应时间很关键或在正常系统运行期间不应禁止中断时,通常使用不可屏蔽中断。这样的用途包括报告不可恢复的硬件错误,系统调试以及对诸如系统重置之类的情况进行分析和处理。
Eg:
Trap of 8085
可屏蔽和不可屏蔽中断之间的区别:
SR.NO. | Maskable Interrupt | Non Maskable Interrupt |
---|---|---|
1 | Maskable interrupt is a hardware Interrupt that can be disabled or ignored by the instructions of CPU. | A non-maskable interrupt is a hardware interrupt that cannot be disabled or ignored by the instructions of CPU. |
2 | When maskable interrupt occur, it can be handled after executing the current instruction. | When non-maskable interrupts occur, the current instructions and status are stored in stack for the CPU to handle the interrupt. |
3 | Maskable interrupts help to handle lower priority tasks. | Non-maskable interrupt help to handle higher priority tasks such as watchdog timer. |
4 | Maskable interrupts used to interface with peripheral device. | Non maskable interrupt used for emergency purpose e.g power failure, smoke detector etc . |
5 | In maskable interrupts, response time is high. | In non maskable interrupts, response time is low. |
6 | It may be vectored or non-vectored. | All are vectored interrupts. |
7 | Operation can be masked or made pending. | Operation Cannot be masked or made pending. |
8 | RST6.5, RST7.5, and RST5.5 of 8085 are some common examples of maskable Interrupts. | Trap of 8085 microprocessor is an example for non-maskable interrupt. |