中断是由 CPU 以外的组件引起的事件。它指示需要立即注意的外部事件的 CPU。中断异步发生。可屏蔽中断和不可屏蔽中断是两种类型的中断。
1. 可屏蔽中断:
可由 CPU 指令禁用或忽略的中断称为可屏蔽中断。中断要么是边沿触发的,要么是电平触发的,或者是电平触发的。
Eg:
RST6.5,RST7.5,RST5.5 of 8085
2. 不可屏蔽中断:
不能被 CPU 指令禁止或忽略的中断称为不可屏蔽中断。不可屏蔽中断通常用于响应时间很关键或在正常系统操作期间不应禁止中断的情况。此类用途包括报告不可恢复的硬件错误、系统调试和分析以及处理系统重置等物种情况。
Eg:
Trap of 8085
可屏蔽中断和不可屏蔽中断的区别:
SR.NO. | Maskable Interrupt | Non Maskable Interrupt |
---|---|---|
1 | Maskable interrupt is a hardware Interrupt that can be disabled or ignored by the instructions of CPU. | A non-maskable interrupt is a hardware interrupt that cannot be disabled or ignored by the instructions of CPU. |
2 | When maskable interrupt occur, it can be handled after executing the current instruction. | When non-maskable interrupts occur, the current instructions and status are stored in stack for the CPU to handle the interrupt. |
3 | Maskable interrupts help to handle lower priority tasks. | Non-maskable interrupt help to handle higher priority tasks such as watchdog timer. |
4 | Maskable interrupts used to interface with peripheral device. | Non maskable interrupt used for emergency purpose e.g power failure, smoke detector etc . |
5 | In maskable interrupts, response time is high. | In non maskable interrupts, response time is low. |
6 | It may be vectored or non-vectored. | All are vectored interrupts. |
7 | Operation can be masked or made pending. | Operation Cannot be masked or made pending. |
8 | RST6.5, RST7.5, and RST5.5 of 8085 are some common examples of maskable Interrupts. | Trap of 8085 microprocessor is an example for non-maskable interrupt. |