1. 单周期数据路径：
Single Datapaths 相当于原来的单周期 datapath 数据存储器只有一个地址输入。实际的内存操作可以通过 MemRead 和 MemWrite 控制信号来确定。指令和数据有单独的存储器 有 2 个用于基于 PC 的计算的加法器和一个 ALU。控制信号相同。
2. 管道数据路径：
流水线的目标是允许同时执行多条指令。我们可能需要在一个循环中执行多个操作。递增PC并同时添加寄存器。获取一条指令，而另一条指令读取或写入数据。
与单周期数据路径一样，流水线处理器需要复制同一时钟周期所需的硬件元素。
Single Datapath 和 Pilpeline Datapath 之间的差异：
| S.No. | Single Cycle Datapath | Pipleline Datapath |
|---|---|---|
| 1 | Instructions are not subdivided | Instructions are divided into one per stage |
| 2 | Clock cycles are long enough for the lowest instruction | Clock cycles are short but long enough for the lowest instruction |
| 3 | There are only 1 instruction that can be executed at the same time. | There are as many instructions as pipeline stages |
| 4 | There is 1 cycle per instruction, i, e., CPI = 1 | There is a fixed number of clock cycles per instruction, one for each pipeline stage, i.e., CPI = k |
| 5 | Control unit generates signals for the entire instruction. | Control unit generates signals for the entire instruction; these signals are propagated from one pipeline stage to another via the pipeline registers. |
| 6 | There is duplicate hardware, because we can use a functional unit for at most one subtask per instruction. | There is duplicate hardware, so that there are no restrictions on which instructions can be in the pipeline simultaneously. |
| 7 | Extra registers are not required. | Extra registers are requeired to provide the results of one pipeline stage to the next pipeline stage. |
| 8 | Performance is baseline. | Performance is moderately faster to significantly faster than a single cycle. |