1. 单周期数据路径:
Single Datapaths 相当于原来的单周期 datapath 数据存储器只有一个地址输入。实际的内存操作可以通过 MemRead 和 MemWrite 控制信号来确定。指令和数据有单独的存储器。有 2 个用于基于 PC 的计算的加法器和一个 ALU。控制信号相同。
2. 多周期数据路径:
多周期数据路径将指令分解为单独的步骤。每一步都需要一个时钟周期 每个功能单元在一条指令中可以多次使用,只要在不同的时钟周期中使用即可。它减少了所需的硬件数量。它减少了平均指令时间。
单周期和多周期数据路径之间的差异:
S.No. | Single Cycle Datapath | Multiple Cycle Datapath |
---|---|---|
1 | Instructions are not subdivided. | Instructions are divided into artitoray number of steps. |
2 | Clock cycles are long enough for the lowest instruction. | Clock cycles are short but long enough for the lowest instruction. |
3 | There are only 1 instruction that can be executed at the same time. | There are only 1 instruction that can be executed at the same time. |
4 | There is 1 cycle per instruction, i, e., CPI = 1. | There is a variable number of clock cycles per instructions. |
5 | Control unit generates signals for the entire instruction. | Control unit generates signals for the instruction’s current step and keeps track of the current step. |
6 | There is duplicate hardware, because we can use a functional unit for at most one subtask per instruction. | There is no duplicate hardware, because the instructions generally are broken into single FU steps. |
7 | Extra registers are not required. | Extra registers are required to hold the result of one step for use in the next step. |
8 | Performance is baseline. | Performance is slightly slower to mederaletly faster than single cycle, latter when the instructions steps are well balanced and a significantly fractions of the instructions take less than the maximum number of cycles. |