Makefile For Loop

Makefiles are a popular way to automate the build process for software projects. They allow developers to define a set of rules and dependencies for compiling and linking code, making it easier to manage complex projects. One of the most powerful features of Makefiles is the ability to use loops to iterate over a set of targets.

Basic Syntax

The basic syntax for a for loop in a Makefile is as follows:

for variable in list
    ...
endfor

The variable parameter is a placeholder for a variable name (e.g. i, j, k, etc.) and the list parameter is a comma-separated list of values to iterate over.

For example, to create a loop that prints the numbers 1 to 5, you could use the following code:

numbers := 1 2 3 4 5

for i in $(numbers)
    echo $$i
endfor

Note that the $$ symbol is used to escape the $ character, which is a special character in Makefiles.

Using Loops to Build Targets

Loops can also be used to build targets dynamically based on a set of dependencies. For example, suppose we have a set of C source files in a directory and we want to build an executable for each file using the gcc compiler.

We can use a loop in our Makefile to automate this process, like so:

SOURCES := $(wildcard *.c)
OBJECTS := $(SOURCES:.c=.o)
EXECS := $(SOURCES:.c=)

all: $(EXECS)

$(EXECS): % : %.o
    gcc -o $@ $<

$(OBJECTS): %.o : %.c
    gcc -c $<

clean:
    rm -f $(EXECS) $(OBJECTS)
    
for exec in $(EXECS)
    $(info Building executable: $(exec))
endfor

In this example, we use the $(wildcard) function to find all C source files in the current directory, and then create a set of object files and executable targets based on the names of the source files.

The $(EXECS) target depends on all of the executable targets we want to build, and the % symbol is used as a wildcard to match the name of each executable.

The $(OBJECTS) target depends on all of the object files we need to build, and again the % symbol is used as a wildcard to match the name of each object file.

Finally, we use a loop to print a message for each executable target we build. This can be helpful for debugging and keeping track of progress during the build process.

Conclusion

In conclusion, loops are a powerful tool in Makefiles that can help automate many aspects of the build process for software projects. By using loops to iterate over target names and dependencies, developers can create flexible and efficient build systems that can handle even the most complex projects.