📜  Verilog 和 SystemVerilog 的区别

📅  最后修改于: 2021-09-15 01:54:16             🧑  作者: Mango

1. Verilog :
Verilog 是一种硬件描述语言 (HDL)。它是一种计算机语言,用于描述电子电路的结构和行为。 1983 年,Verilog 语言在 Gateway Design Automation Inc 开始作为硬件建模的专有语言,后来在 1995 年成为 IEEE 标准 1364,并开始得到更广泛的应用。 Verilog 基于模块级测试平台。

2. SystemVerilog :
SystemVerilog 是硬件描述语言 (HDL) 和硬件验证语言 (HVL) 的组合,并称为 HDVL。意味着它描述了电子电路的结构和行为,并验证了用硬件描述语言编写的电子电路。 SystemVerilog 作为 Verilog 的超集,在 2005 年对 Verilog 语言进行了大量扩展,成为 IEEE 标准 1800,并在 2012 年再次更新为 IEEE 1800-2012 标准。 SystemVerilog 基于本质上更具动态性的类级测试平台。

Verilog 和 SystemVerilog 的区别:

S.No. VERILOG SYSTEMVERILOG
01. Verilog is a Hardware Description Language (HDL). SystemVerilog is a combination of both Hardware Description Language (HDL) and Hardware Verification Language (HVL).
02. Verilog language is used to structure and model electronic systems. SystemVerilog language is used to model, design, simulate, test and implement electronic system.
03. It supports structured paradigm. It supports structured and object oriented paradigm.
04. Verilog is based on module level testbench. SystemVerilog is based on class level testbench.
05. It is standardized as IEEE 1364. It is standardized as IEEE 1800-2012.
06. Verilog is influenced by C language and Fortran programming language. SystemVerilog is based on Verilog, VHDL and c++ programming language.
07. It has file extension .v or .vh It has file extension .sv or .svh
08. It supports Wire and Reg datatype. It supports various datatypes like enum, union, struct, string, class.
09. It is based on hierarchy of modules. It is based on classes.
10. It was began in 1983 as proprietary language for hardware modelling. It was originally intended as an extension to Verilog in the year 2005.